The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a process for fabricating a field effect transistor having a doped gate electrode, such as a silicon germanium (SiGe) gate electrode for example, with prevention of contamination of an implantation chamber from the bombardment of the implantation ions with the gate electrode.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension 104 and a source extension 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension 104 and the source extension 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate electrode 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate electrode 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where the MOSFET 100 is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the gate electrode 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (Si3N4), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the gate electrode 118 and the gate dielectric 116.
As the dimensions of the MOSFET 100 are scaled down to tens of nanometers, short-channel effects degrade the performance of the MOSFET 100. Short-channel effects that result due to the short length of the channel between the drain extension 104 and the source extension 106 of the MOSFET 100 are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the MOSFET 100 become difficult to control with bias on the gate electrode 118 with short-channel effects which may severely degrade the performance of the MOSFET.
As the dimensions of the MOSFET 100 are further scaled down to tens of nanometers, short channel effects are more likely to disadvantageously affect the operation of the MOSFET 100, as known to one of ordinary skill in the art of integrated circuit fabrication. Referring to FIG. 1, to prevent short channel effects as the dimensions of the MOSFET 100 are further scaled down, halo regions 105 and 107 are formed by the drain extension junction 104 and the source extension junction 106 in the semiconductor substrate 102. A drain halo region 105 is formed by the drain extension junction 104, and a source halo region 107 is formed by the source extension junction 106.
The halo regions 105 and 107 are implanted with a halo dopant that is opposite in type to the dopant within the drain and source extension junctions 104 and 106. For example, when the drain and source extension junctions 104 and 106 are implanted with an N-type dopant for an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor), the halo regions 105 and 107 are implanted with a P-type dopant for preventing short channel effects of the NMOSFET. On the other hand, when the drain and source extension junctions 104 and 106 are implanted with a P-type dopant for a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor), the halo regions 105 and 107 are implanted with an N-type dopant for preventing short channel effects of the PMOSFET. Such halo regions 105 and 107 are known to one of ordinary skill in the art of integrated circuit fabrication.
As the dimensions, including the thickness (i.e., the height), of the gate electrode 118 are further scaled down, resistance of the gate electrode 118 may limit the device speed of the MOSFET 100. To minimize resistance of the gate electrode, the gate electrode 118 is formed with a doped semiconductor material such as silicon doped with germanium instead of just polysilicon. For example, the gate electrode 118 is comprised of silicon germanium (SiGe) having a germanium concentration in a range of from about 10 atomic percent to about 60 atomic percent.
Such a silicon germanium gate electrode 118 is advantageous because an N-type or P-type dopant has a higher activation rate within silicon germanium (than in just polysilicon), as known to one of ordinary skill in the art of integrated circuit fabrication, to minimize the resistance of the silicon germanium gate electrode 118. In addition, a silicon germanium gate electrode 118 effectively suppresses diffusion of an N-type or P-type dopant, such as boron for example, from the silicon germanium gate electrode 118 into the gate dielectric 116 and the semiconductor substrate 102. Such diffusion of dopant from the gate electrode 118 into the gate dielectric 116 and the semiconductor substrate 102 disadvantageously affects the threshold voltage of the MOSFET 100.
Referring to FIG. 2, to further enhance the control of the electrical characteristics of a MOSFET as the dimensions of the MOSFET are scaled down, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 150 is fabricate in SOI (semiconductor on insulator) technology. In SOI technology, a layer of buried insulating material 132 is deposited on the semiconductor substrate 102. The layer of buried insulating material 132 is typically comprised of silicon dioxide (SiO2) when the semiconductor substrate 102 is comprised of silicon. In addition, a thin silicon film 134 is deposited on the layer of buried insulating material 132.
A gate dielectric 136 and a gate electrode 138 are formed on the thin silicon film 134. A drain and source dopant is implanted into exposed regions of the thin silicon film 134 to form a drain 142 and a source 144 of the MOSFET 150. A channel region of the MOSFET 150 is the portion of the thin silicon film 134 disposed between the drain 142 and the source 144 and disposed below the gate dielectric 136. The silicon film 134 is relatively thin having a thickness in a range of from about 5 nanometers to about 20 nanometers for example. Thus, the channel region of the MOSFET 150 is fully depleted during operation of the MOSFET 150 with improved control of electrical characteristics of the MOSFET 150, as known to one of ordinary skill in the art of integrated circuit fabrication. Thus, the fully depleted channel region of the MOSFET 150 formed in SOI technology minimizes undesired short-channel effects, as known to one of ordinary skill in the art of integrated circuit fabrication.
The silicon film 134 is typically not doped such that the channel region of the MOSFET 150 between the drain 142 and the source 144 is fully depleted during operation of the MOSFET 150. However, the threshold voltage of the MOSFET 150 may be difficult to adjust without doping the channel region of the MOSFET 150. In that case, using silicon germanium for the gate electrode 138 is advantageous for adjusting the threshold voltage of the MOSFET 150. The concentration of germanium within the gate electrode 138 is adjusted in a range of from about 10 atomic percent to about 60 atomic for affecting the threshold voltage of the MOSFET 150.
Despite such advantages of using silicon germanium for the gate electrode 118 or 138, the germanium from the gate electrode 118 or 138 may contaminate an ion implantation chamber. Referring to FIG. 3 for example, during formation of the halo regions 105 and 107, a halo dopant is implanted at an angle toward the sidewalls of the silicon germanium gate electrode 118 or 138. Angled implantation processes are known to one of ordinary skill in the art of integrated circuit fabrication. Implantation ions comprising the halo dopant bombard the top surface and the sidewalls of the silicon germanium gate electrode 118 or 138 such that pieces of silicon germanium are chipped off from the gate electrode 118 or 138 to disadvantageously contaminate the implantation chamber.
Thus, a mechanism for fabricating a field effect transistor with a doped gate electrode without contaminating the implantation chamber is desired.
Accordingly, in a general aspect of the present invention, a doped gate electrode, such as a silicon germanium gate electrode, is formed with liner dielectric structures at the sidewalls of the doped gate electrode and with an amorphous semiconductor structure and a hardmask structure on top of the doped gate electrode. Such structures prevent bombardment of implantation ions with the doped gate electrode during an implantation process to prevent contamination of the implantation chamber.
In one embodiment of the present invention, for fabricating a field effect transistor on a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate, a layer of doped gate electrode material is deposited on the layer of gate dielectric material, a layer of amorphous semiconductor material is deposited on the layer of doped gate electrode material, and a layer of hardmask dielectric material is deposited on the layer of amorphous semiconductor material. A masking material is patterned to form a masking structure, and any portion of the layer of hardmask dielectric material, the layer of amorphous semiconductor material, the layer of doped gate electrode material, and the layer of gate dielectric material, not under the masking structure, are etched away.
The hardmask dielectric material remaining under the masking structure forms a hardmask structure. The amorphous semiconductor material remaining under the hardmask structure forms an amorphous semiconductor structure. The doped gate electrode material remaining under the amorphous semiconductor structure forms a doped gate electrode of the field effect transistor. The gate dielectric material remaining under the doped gate electrode forms a gate dielectric of the field effect transistor. The gate dielectric, the doped gate electrode, the amorphous semiconductor structure, and the hardmask structure form a gate stack.
The masking structure is removed from top of the hardmask structure. Liner dielectric structures are formed on sidewalls of the gate stack. A dopant is implanted into exposed regions of the semiconductor substrate after forming the liner dielectric structures on the sidewalls of the gate stack.
The present invention may be used to particular advantage when the doped gate electrode material is comprised of silicon doped with germanium having a germanium concentration in a range of from about 10 atomic percent to about 60 atomic percent, when the layer of amorphous semiconductor material is comprised of amorphous silicon, and when the hardmask material is comprised of silicon nitride (Si3N4). In addition, the liner dielectric structures may be comprised of silicon dioxide (SiO2) having a thickness in a range of from about 100 angstroms to about 200 angstroms. In that case, the liner dielectric structures are advantageously formed from a CVD (chemical vapor deposition) process using a temperature of less than about 400xc2x0 Celsius to prevent recrystallization of the amorphous silicon.
In this manner, the liner dielectric structures on the sidewalls of the gate stack prevent bombardment of implantation ions against the sidewalls of the doped gate electrode to prevent contamination of the implantation chamber. In addition, the amorphous semiconductor structure on top of the doped gate electrode prevents out-diffusion of the germanium from the doped gate electrode since germanium substantially does not diffuse through amorphous silicon. The hardmask structure on the amorphous silicon structure prevents bombardment of implantation ions against the top of a semiconductor material of the gate stack to further prevent contamination of the implantation chamber.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.